This application claims the benefit of Korean Patent Application No. 10-2004-0112906, filed on Dec. 27, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Disclosure
The present disclosure relates to a Ge precursor, a GST thin layer formed using the same, and a method of manufacturing the GST thin layer, and more particularly, to a Ge precursor for low temperature deposition containing Ge, N, and Si, a GST thin layer formed at a low temperature using the Ge precursor, a phase-change memory device including the GST thin layer, and a method of manufacturing the GST thin layer.
2. Description of the Related Art
Phase-change materials exist in a crystalline state or an amorphous state according to temperature. A phase-change material has a lower resistance and a more ordered atomic arrangement in a crystalline state than in an amorphous state. A phase-change material can be reversibly transformed from the crystalline state to the amorphous state. In other words, a phase-change material can transform from the crystalline state to the amorphous state, and from the amorphous state to the crystalline state. Such characteristics, that is, reversible phase change and different resistances of different states, are used in phase-change random access memory (PRAM) devices.
Typically, PRAM includes a phase-change layer electrically connected to a source region or drain region of a transistor via a contact plug. PRAM operates based on the change in resistance resulting from the change of the crystalline structure of a phase-change layer. FIG. 1 is a sectional view of a conventional PRAM.
Referring to FIG. 1, a first impurity region 11a and a second impurity region 11b are formed in a semiconductor substrate 10. A gate insulating layer 12 contacts the first impurity region 11a and the second impurity region 11b. A gate electrode layer 13 is formed on the gate insulating layer 12. The first impurity region 11a refers to a source, and the second impurity region 11b refers to a drain.
An insulating layer 15 is formed on the first impurity region 11a, the gate electrode layer 13, and the second impurity region 11b. A contact plug 14 penetrates through the insulating layer 15 and contacts the second impurity region 11b. A lower electrode 16 is formed on the contact plug 14, and a phase-change layer 17 and an upper electrode 18 are sequentially formed on the lower electrode 16.
A method of storing data in the PRAM will now be described. When a current is supplied through the second impurity region 11b and the lower electrode 16, joule heating occurs at an interface region between the lower electrode 16 and the phase-change layer 17 such that the crystal structure of the phase change layer 17 is changed. In other words, the crystal structure of the phase-change layer 17 can be changed by properly changing the applied current. Such a phase change between a crystalline phase and an amorphous phase leads to a change in resistance, which enables identification of stored binary data values.
Up to now, various phase-change materials available for use in memory devices have been developed, such as a GST(GeSbTe) alloy. For example, Korean Patent No. 2004-0100499 discloses a semiconductor memory device including a chalcogenide material layer.
In order to improve the performance of memory devices, power consumption must be decreased. However, a PRAM including a conventional phase-change GST has a high reset current, which is a current needed to change the state of a phase-change material from a crystalline state to an amorphous state.
FIG. 2 is a graph illustrating a heating temperature for reset/set programming of a memory device including a Ge2Sb2Te5 phase-change layer.
Referring to FIG. 2, when setting programming, i.e., the transition from an amorphous state to a crystalline state can be realized at a temperature below the melting point (Tm) of GST layer for a predetermined time. On the other hand, when reset programming, i.e., the transition from the crystalline state to the amorphous state can be realized by heating to the melting point (Tm) of GST layer and then quenching. In order to increase the temperature to Tm, a large amount of a current must be supplied, which is undesirable for a highly integrated memory device.